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BittWare Announces SmartNIC Shell for Building FPGA-powered 100G NICs

BittWare Announces SmartNIC Shell for Building FPGA-powered 100G NICs
12/04/2018

BittWare has announced SmartNIC Shell, a suite of IP modules for building 100G network interface controllers (NICs) using FPGAs for hardware packet processing. Users can fully customise Shell components, including a Match/Action pipeline with features including Xilinx SDNet support and the P4 network programming language. For host application interaction the Arkville DPDK IP is integrated for kernel bypass. SmartNIC Shell allows teams to avoid the time-consuming process of building core NIC functions into an FPGA, allowing them to focus resources on their own application.

The SmartNIC Shell is targeted at low-profile and standard-height BittWare boards using Xilinx UltraScale+ FPGAs. The initial release provides 1x 100GbE and DPDK host interaction through the PCIe Gen3 x16 interface. DPDK kernel bypass utilizes the Arkville IP core and provides dropless data transfer though an UltraRAM FIFO buffer on the FPGA. Precision timestamping is also provided including 1588-compatible clock adjustments using TimeServo IP.

With the rapid growth in demand for high-bandwidth networking, more FPGA solutions will be required for applications like cyber security and 5G. BittWare’s new SmartNIC Shell offers teams creating solutions for these applications a new alternative to creating their own network stack, allowing them to better focus their resources and get to market faster.

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